1. Field of the Invention
The present invention relates to a semiconductor memory device provided with a plurality of memory mats formed by dividing a memory array or a memory block, and subword drivers (SWDs) connected to each memory mat, and a subword driver driving system.
2. Description of the Related Art
Hitherto, as this type of semiconductor memory device, there has been known the dynamic RAM (hereinafter referred to as “DRAM”) disclosed in Japanese Unexamined Patent Application Publication No. 9-36328 (JP-A). In the DRAM, the storage area on a chip is divided into a plurality of memory blocks, each memory block being divided into a plurality of memory mats. In this case, each memory mat has a plurality of memory cells. In a DRAM of this type, each memory mat is surrounded by a sense amplifier assembly and a subword driver (SWD) assembly. The sense amplifier assemblies are disposed at the positions where they can be connected to column selection lines and bit lines arranged in the direction of columns. The SWD assemblies are disposed at the positions where they can be connected to main word lines and subword lines arranged in the direction of rows, and include a plurality of SWDs. Providing the SWD assemblies allows the operating storage area to be accommodated in a small area, and makes it possible to reduce power comsumption and to operate at a high speed.
Moreover, each SWD assembly includes a plurality of subword driver circuits, and each subword driver circuit is connected to a main word line and a subword line arranged in the direction of rows, as mentioned above, and also connected to a subword selection line (hereinafter referred to also as an “FX line”) that extends from a subword selection decoder. Thus, each subword driver circuit selects a main word line and a subword selection line to selectively activate a subword line so as to activate the memory cell associated with the subword line.
For this type of DRAM, it has been proposed to share a plurality of subword selection lines by a plurality of memory mats. In this case, a driving system may be adopted, in which a subword selection line is disposed between two memory mat arrays disposed in the direction of columns with an interval provided therebetween, and the subword selection line is branched or divided in the direction of arrays to connect them to the subword drivers associated with the memory mats disposed on both sides of the subword selection line. The drivers are driven by subword selection signals on the subword selection line. In this case, subword selection signals (FX signals) are sent from a subword selection decoder to the subword selection line.
As described above, if the FX branching or dividing drive method is adopted, then the capacity of the DRAM and the number of memory mats to be selected by a single subword selection line will inevitably increase. If the number of memory mats increases, as in this case, then the number of the subword driver circuits to be selected by the same subword selection line tends to dramatically increase.
Conventionally, a drive method is adopted such that a subword selection signal (FXT) of a single polarity is sent from a subword selection decoder to each subword selection line. In such a drive method, a delay in operation is inevitably caused to occur between a subword driver circuit near the subword selection decoder and a subword driver circuit far away from the subword selection decoder, as the number of memory mats increases.
There has been proposed another branching drive method in which a subword selection signal of a single polarity from a subword selection decoder is inverted each time it is handed down to another subword driver circuit so as to use two subword selection signals (FXT and FXB) having the positive polarity and the negative polarity, respectively, thus the subword driver circuits are driven.
Using this branching drive method, however, does not solve the problem of the unignorable influences of wiring resistance and load capacitances, as the memory capacity increases. The experiments carried out by the assignee have revealed that an increase in wiring resistance or the like results from an increase in the load imposed by on FXBs of the selection signals increases.